The Elements of Computing Systems: Building a Modern Computer from First Principles (50 page)

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Authors: Noam Nisan,Shimon Schocken

BOOK: The Elements of Computing Systems: Building a Modern Computer from First Principles
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The simulator’s builtIn directory contains executable versions of all the chips specified in the book, except for the highest-level chips (CPU, Memory, and Computer). Hence, one may construct and test every chip mentioned in the book before all, or even any, of its lower-level chip parts have been implemented: The simulator will automatically invoke their built-in versions instead. Likewise, if a lower-level chip Xxx has been implemented by the user in HDL, the user can still force the simulator to use its built-in version instead, by simply moving the Xxx.hdl file out from the current directory. Finally, in some cases the user (rather than the simulator) may want to load a built-in chip directly, for example, for experimentation. To do so, simply navigate to the tools/builtIn directory—a standard part of the hardware simulator environment—and select the desired chip from there.
A.4 Chip Header (Interface)
The header of an HDL program has the following format:
■
CHIP declaration:
The CHIP keyword is followed by the chip name. The rest of the HDL code appears between curly brackets.
■
Input pins:
The IN keyword is followed by a comma-separated list of input pin names. The list is terminated with a semicolon.
■
Output pins:
The OUT keyword is followed by a comma-separated list of output pin names. The list is terminated with a semicolon.
 
Input and output pins are assumed by default to be single-bit wide. A multi-bit bus can be declared using the notation pin
name
[
w
] (e.g., a [3] in EQ3.hdl). This specifies that the pin is a bus of width w. The individual bits in a bus are indexed 0...w—1, from right to left (i.e., index 0 refers to the least significant bit).
A.5 Chip Body (Implementation)
A.5.1 Parts
A typical chip consists of several lower-level chips, connected to each other and to the chip input/output pins in a certain “logic” (connectivity pattern) designed to deliver the chip functionality. This logic, written by the HDL programmer, is described in the chip body using the format:
PARTS:
Where each internal chip part statement describes one internal chip with all its connections, using the syntax:
Where each connection is described using the syntax:
(Throughout this appendix, the presently defined chip is called chip, and the lower-level chips listed in the PARTS section are called
parts
).
A.5.2 Pins and Connections
Each
connection
describes how one pin of a part is connected to another pin in the chip definition. In the simplest case, the programmer connects a part’s pin to an input or output pin of the chip. In other cases, a part’s pin is connected to another pin of another part. This internal connection requires the introduction of an
internal pin
, as follows:
 
Internal Pins
In order to connect an output pin of one part to the input pins of other parts, the HDL programmer can create and use an internal pin, say v, as follows:
Internal pins (like v) are created as needed when they are specified the first time in the HDL program, and require no special declaration. Each internal pin has fan-in 1 and unlimited fan-out, meaning that it can be fed from a single source only, yet it can feed (through multiple connections) many other parts. In the preceding example, the internal pin v simultaneously feeds both Part2 (through in) and Part3 (though a and b).
Input Pins
Each input pin of a part may be fed by one of the following sources:
• an input pin of the chip
• an internal pin
• one of the constants true and false, representing 1 and 0, respectively
Each input pin has fan-in 1, meaning that it can be fed by one source only. Thus Part (in1=v, in2=v, ...) is a valid statement, whereas Part (in1=v, in1=u, ...) is not.
 
Output Pins
Each output pin of a part may feed one of the following destinations:
• an output pin of the chip
• an internal pin
A.5.3 Buses
Each pin used in a connection—whether input, output, or internal—may be a multi-bit bus. The widths (number of bits) of input and output pins are defined in the chip header. The widths of internal pins are deduced implicitly, from their connections.
In order to connect individual elements of a multi-bit bus input or output pin, the pin name (say x) may be subscripted using the syntax x[i] or x[i...j]=v, where v is an internal pin. This means that only the bits indexed
i
to
j
(inclusive) of pin
x
are connected to the specified internal pin. An internal pin (like v above) may not be subscripted, and its width is deduced implicitly from the width of the bus pin to which it is connected the first time it is mentioned in the HDL program.
The constants true and false may also be used as buses, in which case the required width is deduced implicitly from the context of the connection.
Example
Suppose now that Foo is invoked by another chip using the part statement:
where v is a previously declared 3-bit internal pin, bound to some value. In that case, the connections in[2..4]=v and in [6..7]=true will bind the in bus of the Foo chip to the following values:
Now, let us assume that the logic of the Foo chip returns the following output:

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